The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Sep. 04, 2017
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Gen Watari, Chigasaki Kanagawa, JP;

Masato Sugita, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01); H01L 21/00 (2006.01); H01L 23/552 (2006.01); H01Q 1/52 (2006.01); H01L 23/60 (2006.01); H01L 25/18 (2006.01); H01L 23/528 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/60 (2013.01); H01L 23/5286 (2013.01); H01L 25/18 (2013.01); H01L 23/49816 (2013.01);
Abstract

A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer. The second ground layer is electrically connected to the first ground layer through one of the solder balls.


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