The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Sep. 08, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Kenji Konomi, Nagoya, JP;

Manabu Takakuwa, Tsu, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G01B 11/24 (2006.01); G01B 11/06 (2006.01); H01L 21/033 (2006.01); G06T 7/00 (2017.01); G02B 21/26 (2006.01); H01L 23/544 (2006.01); G02B 21/00 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); G01B 11/0616 (2013.01); G01B 11/24 (2013.01); G02B 21/0016 (2013.01); G02B 21/26 (2013.01); G06T 7/001 (2013.01); H01L 21/0337 (2013.01); H01L 23/544 (2013.01); G06T 2207/20021 (2013.01); G06T 2207/30148 (2013.01); G06T 2207/30204 (2013.01); H01L 23/562 (2013.01); H01L 2223/54426 (2013.01);
Abstract

According to one embodiment, there is provided a measurement method. The method includes acquiring layer information related to a plurality of layers to be superimposed for each of a plurality of shot regions on a substrate. The method includes dividing the plurality of shot regions into a plurality of groups corresponding to a layer attribute based on the acquired layer information. The method includes deciding a measurement condition of a measuring apparatus for each of the plurality of groups. The plurality of layers are sequentially stacked on the substrate to manufacture a semiconductor device.


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