The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Feb. 26, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Yasuhiro Hirashima, Kawasaki Kanagawa, JP;

Mami Kakoi, Yokohama Kanagawa, JP;

Shinya Okuno, Fujisawa Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); H01L 25/065 (2006.01); G11C 29/50 (2006.01); G11C 7/10 (2006.01); G11C 7/20 (2006.01); G11C 29/02 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
G11C 5/025 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/20 (2013.01); G11C 29/022 (2013.01); G11C 29/028 (2013.01); G11C 29/50008 (2013.01); H01L 25/0657 (2013.01); G11C 2207/2254 (2013.01); H01L 25/50 (2013.01);
Abstract

A semiconductor memory device includes a plurality of memory chips that are stacked above one another and connected to each other through a through via, an interface chip that is connected to the plurality of memory chips, and a plurality of first terminals for connection with an external device. The interface chip includes a plurality of second terminals that are connected to the plurality of first terminals, and is capable of receiving a signal that is supplied from the external device through the first and second terminals, and stores configuration information according to which a set number of the second terminals are designated for receiving control signals for the plurality of memory chips.


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