The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Sep. 26, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jeffrey C. Hanscom, Poughkeepsie, NY (US);

Tynan J. Garrett, Poughkeepsie, NY (US);

John M. Pritz, Mercer Island, WA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4282 (2013.01); G06F 13/4027 (2013.01); H04L 69/22 (2013.01);
Abstract

A system includes an input/output adapter operable to receive packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet on a first pipeline and a second packet on a second pipeline in a same clock cycle. The controller is further operable to route a header portion of the first packet and a header portion of the second packet on a header path to a header buffer including a plurality of physical arrays in parallel through a header buffer write interface having a single offset address. The controller is operable to route a payload portion of the first packet and a payload portion of the second packet on a data path to a data buffer including a plurality of physical arrays in parallel through a data buffer write interface having a single offset address.


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