The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
Apr. 11, 2016
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventors:
Inseok Stephen Choi, San Jose, CA (US);
Byoung Young Ahn, San Jose, CA (US);
Yang Seok Ki, Palo Alto, CA (US);
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/34 (2006.01); G06F 17/30 (2006.01); G06F 12/0871 (2016.01); G06F 12/0873 (2016.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0871 (2013.01); G06F 11/34 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 17/30306 (2013.01); G06F 12/0873 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/163 (2013.01); G06F 2212/214 (2013.01); G06F 2212/284 (2013.01); G06F 2212/305 (2013.01); G06F 2212/313 (2013.01); G06F 2212/465 (2013.01); G06F 2212/601 (2013.01); G06F 2212/604 (2013.01); G06F 2212/7201 (2013.01); G06F 2216/05 (2013.01); Y02D 10/13 (2018.01);
Abstract
In a multi-level cache system, a logic may be responsible for calculating the appropriate sizes for a database cache and a key-value store. Reception circuitry may receive a hit rate for the database cache, a reuse distance for the key-value store, and a user-selected quality of server. An adaption calculator may then calculate a target size for the database cache and a target size for the key-value store. Transmission circuitry may then transmit the target size for the database cache and the target size for the key-value store for use in the multi-level cache system.