The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
Apr. 26, 2017
Western Digital Technologies, Inc., San Jose, CA (US);
Satoshi Yamamoto, San Jose, CA (US);
Western Digital Technologies, Inc., San Jose, CA (US);
Abstract
A multi-layer error correction coding (ECC) parity technique involves dividing a data band into sub-data bands, generating a respective 1-layer sub-data band parity matrix for each associated sub-data band, and generating a respective (q>1)-layer parity matrix for sets of associated adjacent sub-data bands. In the context of a data storage system, the parity generation may be performed at the system-side, and communicated and written to one or more associated data storage devices (DSDs) along with the corresponding data, whereby the DSDs may further associate track ECC information to the written data. In response to receiving at the system-side, location-identifying information about data errors that are not correctable by the DSD using track ECC information, the system may determine an amount of the multi-layer parity information needed to recover the corrupt data, and make a data/parity read request accordingly.