The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Jan. 27, 2016
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventor:

Sunita Jain, Bangalore, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/445 (2018.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 9/4403 (2013.01); G06F 9/445 (2013.01);
Abstract

Methods and systems are disclosed for booting an integrated circuit (IC). In an example implementation, boot read only memory (ROM) code is loaded for execution by a processor circuit of the IC. Via execution of the boot ROM code on the processor circuit, a first boot image is retrieved. A memory address is communicated from a host device to the processor circuit of the IC via an external data bus coupled to a bus interface circuit in the IC. The bus interface circuit is configured by execution of the first boot image to map a first block of addresses on the internal data bus to a second block of addresses on the host device starting at the memory address. When bus mastering is enabled, the processor retrieves a second boot image from the host device by issuing read requests to the first block of addresses.


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