The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Mar. 06, 2017
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Jose Alberto Joao, Austin, TX (US);

Ziqiang Huang, Shanghai, CN;

Alejandro Rico Carro, Austin, TX (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 9/46 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3009 (2013.01); G06F 9/30101 (2013.01); G06F 9/3867 (2013.01); G06F 9/3005 (2013.01); G06F 9/30123 (2013.01); G06F 9/3838 (2013.01); G06F 9/3855 (2013.01); G06F 9/3857 (2013.01); G06F 9/4881 (2013.01);
Abstract

An apparatus comprises processing circuitry for executing instructions of two or more threads of processing, hardware registers to store context data for the two or more threads concurrently, and commit circuitry to commit results of executed instructions of the threads, where for each thread the commit circuitry commits the instructions of that thread in program order. At least one defer buffer is provided to buffer at least one blocked instruction for which execution by the processing circuitry is complete but execution of an earlier instruction of the same thread in the program order is incomplete. This can help to resolve inter-thread blocking and hence improve performance.


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