The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Aug. 28, 2017
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Sota Sakashita, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/57 (2006.01); G06F 9/48 (2006.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); H04W 88/02 (2009.01);
U.S. Cl.
CPC ...
G06F 7/57 (2013.01); G06F 9/3826 (2013.01); G06F 9/3836 (2013.01); G06F 9/3853 (2013.01); G06F 9/4806 (2013.01); G06F 9/30079 (2013.01); G06F 9/5061 (2013.01); H04W 88/025 (2013.01);
Abstract

An arithmetic processing device includes: a decode circuit configured to decode instructions; an execution control circuit configured to hold the instructions decoded by the decode circuit and to output the held instructions in an executable order; an instruction transfer circuit configured to sequentially transfer the instructions sequentially output by the execution control circuit; an instruction generation circuit configured to output, to the instruction transfer circuit, an individual instruction generated from a combined instruction in a case where one of the instructions transferred by the instruction transfer circuit is the combined instruction obtained by combining individual instructions; and an arithmetic execution circuit configured to execute the individual instruction transferred by the instruction transfer circuit.


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