The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Apr. 19, 2018
Applicant:

Anpec Electronics Corporation, Hsinchu, TW;

Inventors:

Yun-Chiang Chang, Hsinchu, TW;

Fu-Chuan Chen, Hsinchu, TW;

Yu-Rong Chen, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); G06F 1/08 (2006.01); H03K 5/24 (2006.01); G06F 1/12 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); H03K 5/24 (2013.01); G06F 1/12 (2013.01); H03K 2005/00019 (2013.01); H03K 2005/00286 (2013.01);
Abstract

A phase adjusting device provided includes a main delay circuit, a first converter, a second converter, a first buck circuit, and a second buck circuit. The main delay circuit receives an input clock signal to generate a main delay signal. The first converter receives the input clock signal to generate a first conversion signal. The second converter is coupled to the main delay circuit to receive the main delay signal and generate a second conversion signal. The first buck circuit is coupled to the first converter to receive the first conversion signal and generate a first buck voltage. The second buck circuit is coupled to the second converter to receive the second conversion signal and generate a second buck voltage. A first phase difference is formed between the main delay signal and the input clock signal.


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