The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Dec. 29, 2017
Applicants:

Hisense Broadband Multimedia Technologies, Co., Ltd., Qingdao, Shandong, CN;

Hisense Broadband Multimedia Technologies, Ltd., Tortola, VG;

Inventor:

Long Zheng, Shandong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/42 (2006.01); H05B 37/02 (2006.01); F21V 29/504 (2015.01); F21V 29/508 (2015.01); F21V 29/83 (2015.01); F21V 5/04 (2006.01); F21V 23/00 (2015.01); H05K 9/00 (2006.01); H04B 10/40 (2013.01); H04B 10/50 (2013.01); H04B 10/85 (2013.01); H04B 15/02 (2006.01);
U.S. Cl.
CPC ...
H05B 37/0209 (2013.01); F21V 5/04 (2013.01); F21V 23/005 (2013.01); F21V 29/504 (2015.01); F21V 29/508 (2015.01); F21V 29/83 (2015.01); G02B 6/4206 (2013.01); G02B 6/428 (2013.01); G02B 6/4214 (2013.01); G02B 6/4246 (2013.01); G02B 6/4251 (2013.01); G02B 6/4256 (2013.01); G02B 6/4274 (2013.01); G02B 6/4283 (2013.01); G02B 6/4292 (2013.01); H04B 10/40 (2013.01); H04B 10/503 (2013.01); H04B 10/85 (2013.01); H04B 15/02 (2013.01); H05K 9/0058 (2013.01);
Abstract

This disclosure relates to optical module. In one implementation, the optical module includes a multi-layer circuit board, a first optical chip, a second optical chip, and a processor, wherein a surface layer on a same side of the circuit board comprises a first row of edge connector pins and a second row of edge connector pins; the first row of edge connector pins comprise a first power pin; the second row of edge connector pins comprise a second power pin; the first power pin is connected to the first optical chip; the second power pin connected to the second optical chip and the processor; the first power pin and the second power pin are aligned along a same direction and are arranged at a same position among the first row of edge connector pins and the second row of edge connector pins; and the first power pin is electrically connected to the second power pin. In another implementation, the first power pin and the second power pin is not electrically connected and wherein the circuit board further comprises a power delay circuit between the second power pin and the processor.


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