The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Apr. 25, 2017
Applicant:

Seagate Technology, Llc, Cupertino, CA;

Inventor:

Robert W. Moss, Windsor, CO (US);

Assignee:

Seagate Technology LLC, Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/58 (2006.01); H04L 9/00 (2006.01); H04L 9/08 (2006.01); G06F 21/75 (2013.01); H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
H04L 9/003 (2013.01); G06F 21/755 (2017.08); H04L 9/0861 (2013.01); H04L 63/1441 (2013.01); G06F 7/588 (2013.01); G06F 2207/7223 (2013.01); G06F 2212/402 (2013.01); H04L 2209/08 (2013.01); H04L 2209/125 (2013.01);
Abstract

Apparatus and method for defending against a side-channel information attack such as a differential power analysis (DPA) attack. In some embodiments, a cryptographic hardware pipeline circuit performs a selected cryptographic function upon a selected set of data over a processing time interval. The pipeline circuit has a sequence of stages connected in series. The stages are enabled responsive to application of an asserted enable signal. An enable interrupt circuit is configured to periodically interrupt the selected cryptographic function to provide a plurality of processing intervals interspersed with the interrupt intervals. At least a selected one of the processing intervals or the interrupt intervals have random durations selected responsive to a series of random numbers.


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