The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2019
Filed:
Sep. 07, 2017
Applicant:
Christopher Julian Travis, Wotton-under-Edge, GB;
Inventor:
Christopher Julian Travis, Wotton-under-Edge, GB;
Assignee:
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/083 (2006.01); H03L 7/23 (2006.01); H04L 7/033 (2006.01); G06F 1/025 (2006.01); H03L 7/07 (2006.01); H03L 7/085 (2006.01); H03L 7/087 (2006.01); H03L 7/099 (2006.01); H03K 3/03 (2006.01); H03L 7/10 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); G06F 1/025 (2013.01); H03K 3/0307 (2013.01); H03L 7/07 (2013.01); H03L 7/083 (2013.01); H03L 7/085 (2013.01); H03L 7/087 (2013.01); H03L 7/0991 (2013.01); H03L 7/0994 (2013.01); H03L 7/0995 (2013.01); H03L 7/10 (2013.01); H03L 7/235 (2013.01); G06F 2211/902 (2013.01);
Abstract
A hybrid numeric-analog clock synchronizer for establishing a clock or carrier locked to a frequency reference. The clock synchronizer is typically a clock multiplier and a jitter attenuator. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip.