The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Oct. 14, 2016
Applicant:

Qorvo Us, Inc., Greensboro, NC (US);

Inventors:

Baker Scott, San Jose, CA (US);

George Maxim, Saratoga, CA (US);

Dirk Robert Walter Leipold, San Jose, CA (US);

Daniel Charles Kerr, Oak Ridge, NC (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/22 (2006.01); H03K 17/16 (2006.01); H03K 17/68 (2006.01); H03F 3/04 (2006.01); H03K 17/14 (2006.01); H03K 17/693 (2006.01);
U.S. Cl.
CPC ...
H03K 17/145 (2013.01); H03K 17/693 (2013.01);
Abstract

An RF switch having an M number of FETs that are stacked in series and coupled between a first end node and a second end node wherein each of the M number of FETs has a gate is disclosed. A resistive network is coupled between a common mode (CM) node and the gate for each of the M number of FETs such that a resistance between the CM node and each gate of the M number of FETs is substantially equal. Biasing circuitry coupled to the CM node is configured to sense a breakdown current flowing through the CM node, and in response to the breakdown current, generate a compensation signal that counters deviations of drain to source voltage across individual ones of the M number of FETs due to an applied RF voltage across the M number of FETs while the RF switch is in an OFF state.


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