The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Aug. 26, 2014
Applicant:

Sharp Kabushiki Kaisha, Osaka-shi, Osaka, JP;

Inventors:

Takao Saitoh, Osaka, JP;

Seiji Kaneko, Osaka, JP;

Yohsuke Kanzaki, Osaka, JP;

Yutaka Takamaru, Osaka, JP;

Keisuke Ide, Osaka, JP;

Takuya Matsuo, Osaka, JP;

Shigeyasu Mori, Osaka, JP;

Hiroshi Matsukizono, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/04 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H01L 29/10 (2006.01); H01L 29/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1248 (2013.01); H01L 29/04 (2013.01); H01L 29/24 (2013.01); H01L 29/7869 (2013.01); H01L 29/78648 (2013.01); H01L 29/78693 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor device includes, a plurality of oxide semiconductor TFTs including a first gate electrode, a first insulating layer in contact with the first gate electrode, an oxide semiconductor layer opposing the first gate electrode via the first insulating layer, a source electrode and a drain electrode which are connected with the oxide semiconductor layer, and an organic insulating layer covering only some of the plurality of oxide semiconductor TFTs, wherein the plurality of oxide semiconductor TFTs include a first TFT which is covered with the organic insulating layer and a second TFT which is not covered with the organic insulating layer, and the second TFT includes a second gate electrode opposing the oxide semiconductor layer via a second insulating layer, the second gate electrode being arranged to overlap with at least a portion of the first gate electrode with the oxide semiconductor layer interposed therebetween.


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