The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Aug. 28, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Min-hwa Chi, San Jose, CA (US);

Hui Zang, Guilderland, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 27/108 (2006.01); H01L 23/535 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 23/535 (2013.01); H01L 27/0886 (2013.01); H01L 27/10826 (2013.01); H01L 27/11 (2013.01); H01L 29/45 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01);
Abstract

FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.


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