The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2019
Filed:
Jun. 19, 2015
Applicant:
Showa Denko K.k., Minato-ku, Tokyo, JP;
Inventors:
Yuzo Sasaki, Hikone, JP;
Susumu Sugano, Hikone, JP;
Assignee:
SHOWA DENKO K.K., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 25/02 (2006.01); H01L 21/02 (2006.01); B24B 9/00 (2006.01); C30B 25/20 (2006.01); C30B 29/36 (2006.01); B24B 9/06 (2006.01); B24D 3/06 (2006.01); B24D 3/28 (2006.01); C30B 33/00 (2006.01); H01L 29/16 (2006.01); H01L 29/34 (2006.01); C23C 16/02 (2006.01); C23C 16/32 (2006.01); C30B 25/18 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02021 (2013.01); B24B 9/00 (2013.01); B24B 9/065 (2013.01); B24D 3/06 (2013.01); B24D 3/28 (2013.01); C23C 16/0254 (2013.01); C23C 16/325 (2013.01); C30B 25/186 (2013.01); C30B 25/20 (2013.01); C30B 29/36 (2013.01); C30B 33/00 (2013.01); H01L 21/02378 (2013.01); H01L 21/02433 (2013.01); H01L 21/02529 (2013.01); H01L 21/02658 (2013.01); H01L 21/02664 (2013.01); H01L 29/1608 (2013.01); H01L 29/34 (2013.01); H01L 29/045 (2013.01);
Abstract
In order to reduce edge defects efficiently and sufficiently, a method for manufacturing a SiC epitaxial wafer according to the present invention is a method for manufacturing a SiC epitaxial wafer that forms a SiC epitaxial layer on top of a SiC single crystal substrate having an off angle, and includes a rough polishing step for subjecting an outer circumferential edge on a starting side of step-flow growth in the SiC single crystal substrate to rough polishing before forming the SiC epitaxial layer; and a final polishing step for further polishing for finish.