The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Oct. 20, 2017
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Lalit Gupta, Cupertino, CA (US);

Jitendra Dasani, Cupertino, CA (US);

Vivek Nautiyal, Milpitas, CA (US);

Fakhruddin Ali Bohra, Austin, TX (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/417 (2006.01); G11C 11/418 (2006.01); H01L 23/528 (2006.01); H01L 27/11 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); H01L 23/528 (2013.01); H01L 27/1104 (2013.01);
Abstract

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.


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