The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Oct. 03, 2017
Applicant:

Cree, Inc., Durham, NC (US);

Inventors:

Mitch Flowers, Apex, NC (US);

Ulf Andre, Hillsborough, NC (US);

Khaled Fayed, Cary, NC (US);

Simon Wood, Raleigh, NC (US);

Assignee:

Cree, Inc., Durham, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); G06F 17/50 (2006.01); H01L 27/088 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01); H01L 29/778 (2006.01); H03F 3/213 (2006.01); H03F 3/195 (2006.01); H03F 1/56 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01); H01L 23/66 (2013.01); H01L 24/06 (2013.01); H01L 24/46 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 29/7787 (2013.01); H03F 1/56 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H01L 2223/6611 (2013.01); H01L 2223/6655 (2013.01); H01L 2223/6683 (2013.01); H01L 2224/04042 (2013.01); H03F 2200/222 (2013.01); H03F 2200/318 (2013.01); H03F 2200/387 (2013.01); H03F 2200/451 (2013.01);
Abstract

A packaged transistor amplifier includes a package having an input lead and an output lead; a transistor stage having a plurality of unit cell transistors that are electrically coupled to the input lead in parallel, each of the unit cell transistors having an output; a first output bond pad that is coupled to a first subset of the outputs of the unit cell transistors by a first feed network; a second output bond pad that is separate from the first output bond pad, the second output bond pad coupled to a second subset of the outputs of the unit cell transistors by a second feed network; a first output bond wire coupled between the first output bond pad and the output lead; and a second output bond wire coupled between the second output bond pad and the output lead. Related design methods are also provided.


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