The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Jan. 04, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Narendhiran Cr, Bangalore, IN;

Satya Kesav Gundabathula, Bangalore, IN;

Muralitharan Jayaraman, Bangalore, IN;

Chittoor Devarajan Sunilkumar, Bangalore, IN;

Satrajit Chakraborty, Bangalore, IN;

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0644 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01);
Abstract

Technology is described herein for performing memory array operations in multiple memory dies in parallel. The memory dies, or groups of non-volatile memory cells on the memory dies, may exhibit different performance times for memory array operations. For example, non-volatile memory cells on one memory die may program more slowly than those on another memory die. The performance times of the memory dies (or groups of the memory cells on different memory dies) may be characterized relative to one another. Memory dies having similar performance times may be placed into the same meta-groups. Meta-groups may be formed at the die, zone, or block level. The meta-groups can be re-formed over the lifetime of the memory system, which can account for changes in performance times over the lifetime of the memory system.


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