The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2019
Filed:
Jan. 27, 2017
Applicant:
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
Inventor:
Tsjerk Hans Hoekstra, Balerno, GB;
Assignee:
Cirrus Logic, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 7/00 (2006.01); H04R 19/00 (2006.01); B81C 1/00 (2006.01); H04R 19/04 (2006.01);
U.S. Cl.
CPC ...
B81B 7/0061 (2013.01); B81C 1/00246 (2013.01); B81C 1/00309 (2013.01); H04R 19/005 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/0315 (2013.01); B81B 2207/012 (2013.01); B81B 2207/015 (2013.01); B81B 2207/07 (2013.01); B81B 2207/096 (2013.01); B81C 2203/0109 (2013.01); H01L 2224/48137 (2013.01); H01L 2924/15151 (2013.01); H04R 19/04 (2013.01); H04R 2201/003 (2013.01); H04R 2499/11 (2013.01); H04R 2499/15 (2013.01);
Abstract
A MEMS transducer package () comprises a package cover () comprising a first bonding region () and an integrated circuit die () comprising a second bonding region () for bonding with the first bonding region of the package cover. The integrated circuit die () comprises an integrated MEMS transducer () and integrated electronic circuitry () in electrical connection with the integrated MEMS transducer. The footprint of the integrated electronic circuitry () at least overlaps the bonding region () of the integrated circuit die ().