The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Apr. 03, 2018
Applicant:

Jtekt Corporation, Osaka-shi, Osaka, JP;

Inventors:

Takehiro Ito, Kuwana-gun, JP;

Satoru Mikamo, Okazaki, JP;

Yuji Fujita, Okazaki, JP;

Assignee:

JTEKT CORPORATION, Osaka-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02P 6/06 (2006.01); B60R 16/02 (2006.01); G06F 11/30 (2006.01); B60L 11/18 (2006.01); B60L 15/00 (2006.01); B60L 15/02 (2006.01); H02P 27/00 (2006.01); H02P 27/04 (2016.01); H02M 1/32 (2007.01);
U.S. Cl.
CPC ...
B60R 16/02 (2013.01); B60L 11/1803 (2013.01); B60L 15/007 (2013.01); B60L 15/02 (2013.01); G06F 11/3055 (2013.01); H02P 27/00 (2013.01); B60L 2240/527 (2013.01); B60L 2260/40 (2013.01); H02M 2001/325 (2013.01); H02P 27/04 (2013.01); Y02T 10/644 (2013.01); Y02T 10/645 (2013.01); Y02T 10/7005 (2013.01);
Abstract

Provided is a vehicle control system that appropriately performs synchronization control for a plurality of control systems. A monitoring circuit generates a command signal when only a first reset signal is input. The monitoring circuit generates a command signal when the state in which only the first reset signal is input is changed to the state in which the input of the first reset signal is stopped. With the command signal, a second clock signal is output to a timer generator as a second timing signal. With the command signal, the second clock signal generated by a second synchronization signal generating circuit is output to a first synchronization signal generating circuit, and a third clock signal generated by the first synchronization signal generating circuit is output to a timer generator as a first timing signal.


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