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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10264674 B1

PDFFull Text
Date of Patent:
Apr. 16, 2019

Filed:

Sep. 18, 2018

Passive element array and printed wiring board

Applicant:

Murata Manufacturing Co., Ltd., Nagaokakyo-shi, Kyoto-fu, JP;

Inventors:

Keito Yonemori, Nagaokakyo, JP;

Hirokazu Yazaki, Nagaokakyo, JP;

Assignee:

MURATA MANUFACTURING CO., LTD., Kyoto, JP;

Attorney:

Keating & Bennett, LLP

Primary Examiner:

Andargie M Aychillhum

Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/16 (2006.01); H01F 27/28 (2006.01); H05K 1/02 (2006.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/11 (2013.01); H01F 27/2804 (2013.01); H05K 1/028 (2013.01); H05K 1/14 (2013.01); H05K 1/165 (2013.01); H05K 1/181 (2013.01); H05K 1/185 (2013.01); H01F 2027/2809 (2013.01); H05K 2201/1003 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10022 (2013.01); H05K 2201/10356 (2013.01);
Abstract

A passive element array includes an element body that includes laminated base material layers, passive elements at different positions in the element body when viewed from a lamination direction of the base material layers, input/output terminals at a first main surface of the element body and connected to one end of each of the passive elements, input/output terminals at a second main surface of the element body and connected to the other end of each of the passive elements, a first ground terminal between the first input/output terminal and the input/output terminal at the first main surface, and a second ground terminal between the input/output terminal and the input/output terminal at the second main surface.

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Yonemori, Keito. (2019). Passive element array and printed wiring board (U.S. Patent No. 10264674). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10264674

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