The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

May. 29, 2018
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

John Paul Lesso, Edinburgh, GB;

David Paul Singleton, Edinburgh, GB;

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/08 (2006.01); H03M 1/34 (2006.01); H03M 1/50 (2006.01);
U.S. Cl.
CPC ...
H03M 1/504 (2013.01); H03M 1/0604 (2013.01); H03M 1/0626 (2013.01); H03M 1/0854 (2013.01); H03M 1/34 (2013.01);
Abstract

This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator () receives an analogue input signal (S) at an input node () and outputs a corresponding time-encoded signal (S) at an output node (). A hysteretic comparator () has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement () arranged to apply filtering to the feedback path. The hysteretic comparator () compares the input signal (S) to the feedback signal (S) with hysteresis. This provides a pulse-width modulated output signal (S) where the duty cycle encodes the input signal (S).


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