The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Aug. 20, 2018
Applicant:

Mosway Technologies Limited, New Territories, Hong Kong, CN;

Inventors:

On Bon Peter Chan, Hong Kong, CN;

Jing Zhu, Jiangsu Province, CN;

Yunwu Zhang, Jiangsu Province, CN;

Assignee:

Mosway Technologies Limited, Fo Tan, New Territories, Hong Kong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/1252 (2006.01); H03K 5/24 (2006.01); H03H 11/04 (2006.01); H03K 19/0948 (2006.01); H03K 3/356 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1252 (2013.01); H03H 11/04 (2013.01); H03K 5/2472 (2013.01); H03K 19/0948 (2013.01); H03K 3/356 (2013.01); H03K 19/20 (2013.01);
Abstract

The present disclosure provides a pulse filtering circuit with two input ports and two output ports, including: a first signal path with a first buffer unit, a first comparison unit, and a first shaping unit; and a second signal path with a second buffer unit, a second comparison unit, and a second shaping unit; each of the first comparison unit and the second comparison unit has four ports, which are a first port, a second port, a third port and a fourth port; the first port of each comparison unit serves as an input control port, the second port of each comparison unit serves as an output port, the third port serves as a fixed potential port, and the fourth port serves as a floating potential input port. The new pulse filtering circuit of the present disclosure may eliminate the common-mode noise signal, especially the dV/dt common-mode noise generated by the power supply, and therefore the circuit has a strong anti-dV/dt noise capability and a small transmission delay, and at the same time reduces the chip area and production costs due to its simple circuit structure.


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