The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Nov. 28, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Rajendrakumar Joish, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/68 (2006.01); H03F 3/19 (2006.01); H03F 1/02 (2006.01); H03F 3/191 (2006.01); H03F 3/45 (2006.01); H03F 1/32 (2006.01); H03F 1/22 (2006.01);
U.S. Cl.
CPC ...
H03F 3/19 (2013.01); H03F 1/0205 (2013.01); H03F 3/191 (2013.01); H03F 3/45098 (2013.01); H03F 3/45103 (2013.01); H03F 1/0277 (2013.01); H03F 1/22 (2013.01); H03F 1/223 (2013.01); H03F 1/3211 (2013.01); H03F 3/45 (2013.01); H03F 2200/111 (2013.01); H03F 2200/294 (2013.01); H03F 2200/451 (2013.01); H03F 2200/546 (2013.01); H03F 2203/45296 (2013.01); H03F 2203/45396 (2013.01);
Abstract

The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.


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