The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Jun. 07, 2016
Applicant:

Linear Technology Corporation, Milpitas, CA (US);

Inventors:

Zhizhong Hou, Fremont, CA (US);

Mitchell E. Lee, San Jose, CA (US);

Daniel J. Eddleman, San Jose, CA (US);

Assignee:

Linear Technology Corporation, Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H02H 9/02 (2006.01); H02H 3/08 (2006.01); H02H 3/087 (2006.01); G05F 1/573 (2006.01);
U.S. Cl.
CPC ...
H02H 9/001 (2013.01); H02H 9/02 (2013.01); H02H 9/025 (2013.01); G05F 1/573 (2013.01); H02H 3/08 (2013.01); H02H 3/087 (2013.01); H02H 9/002 (2013.01); H02H 9/004 (2013.01);
Abstract

In one embodiment, a pass MOSFET is coupled in series between an input voltage and a load, and a bypass capacitor is connected in parallel with the load. In response to a voltage step across the MOSFET, the MOSFET is adaptively controlled to conduct an in-rush current of 2I=2Iduring the bypass capacitorcharging time, where Iis the capacitive current and Iis the load current. This optimizes the in-rush current to achieve a minimum peak temperature of the MOSFET. In one embodiment, a ramp capacitor connected to the drain of the MOSFET is part of a feedback path that tracks the MOSFET drain voltage to control the gate voltage.


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