The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Dec. 07, 2012
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Huilong Zhu, Poughkeepsie, NY (US);

Miao Xu, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/308 (2006.01); H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/02274 (2013.01); H01L 21/308 (2013.01); H01L 21/31111 (2013.01); H01L 29/0843 (2013.01); H01L 29/1083 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/66803 (2013.01); H01L 29/785 (2013.01); H01L 29/7842 (2013.01); H01L 29/7845 (2013.01); H01L 29/7848 (2013.01); H01L 29/7849 (2013.01); H01L 21/26513 (2013.01); H01L 29/165 (2013.01);
Abstract

A FinFET and a method for manufacturing the same are provided. The method includes: patterning a semiconductor substrate to form a ridge; performing ion implantation such that a doped punch-through-stopper layer is formed in the ridge and a semiconductor fin is formed by a portion of the semiconductor substrate disposed above the doped punch-through-stopper layer; forming a gate stack intersecting the semiconductor fin, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin; forming a gate spacer surrounding the gate conductor; and forming source and drain regions in portions of the semiconductor fin at opposite sides of the gate stack.


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