The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Apr. 25, 2014
Applicant:

Hrl Laboratories, Llc, Malibu, CA (US);

Inventors:

Zijian “Ray” Li, Oak Park, CA (US);

Rongming Chu, Newbury Park, CA (US);

Assignee:

HRL Laboratories, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/201 (2006.01); H01L 29/205 (2006.01); H01L 29/47 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 21/0254 (2013.01); H01L 21/02381 (2013.01); H01L 21/02458 (2013.01); H01L 29/201 (2013.01); H01L 29/205 (2013.01); H01L 29/404 (2013.01); H01L 29/4175 (2013.01); H01L 29/42372 (2013.01); H01L 29/475 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/2003 (2013.01);
Abstract

A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.


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