The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2019
Filed:
Mar. 28, 2013
Applicant:
Renesas Electronics Corporation, Kawasaki-shi, JP;
Inventors:
Masayuki Hiroi, Kanagawa, JP;
Takashi Sakoh, Kanagawa, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 27/108 (2006.01); H01L 27/02 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 28/40 (2013.01); H01L 23/5329 (2013.01); H01L 27/0207 (2013.01); H01L 27/10852 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); H01L 28/91 (2013.01); H01L 23/562 (2013.01); H01L 2924/00 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/00014 (2013.01);
Abstract
The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area.