The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Mar. 21, 2018
Applicant:

Ablic Inc., Chiba-shi, Chiba, JP;

Inventor:

Tomomitsu Risaki, Chiba, JP;

Assignee:

ABLIC INC., Chiba, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); G11C 16/04 (2006.01); H01L 29/788 (2006.01); H01L 21/822 (2006.01); C23C 16/24 (2006.01); G11C 11/34 (2006.01); H01L 21/283 (2006.01);
U.S. Cl.
CPC ...
H01L 27/115 (2013.01); C23C 16/24 (2013.01); G11C 11/34 (2013.01); G11C 16/0483 (2013.01); H01L 21/283 (2013.01); H01L 21/822 (2013.01); H01L 29/788 (2013.01); G11C 16/0433 (2013.01);
Abstract

Provided is a semiconductor device which has a non-volatile memory including: a semiconductor substrate; a tunnel insulating film formed on a surface of the semiconductor device; a floating gate formed on the tunnel insulating film; a memory cell transistor drain region and a memory cell transistor source region formed from the surface to an inside of the semiconductor substrate in a vicinity of both ends of the floating gate; a first interface formed between the semiconductor substrate and the tunnel insulating film; and a second interface formed between the floating gate and the tunnel insulating film. The first interface and the second interface form an uneven structure having a curvature that changes at an identical period with respect to a place in sectional view.


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