The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Apr. 01, 2016
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, Tokyo, JP;

Inventors:

Masatoshi Sunamoto, Tokyo, JP;

Ryuji Ueno, Tokyo, JP;

Assignee:

MITSUBISHI ELECTRIC CORPORATION, Chiyoda-Ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); C23C 18/36 (2006.01); C23C 18/42 (2006.01); H01L 21/288 (2006.01); C23C 18/16 (2006.01); C23C 18/32 (2006.01); C23C 18/18 (2006.01); C23C 18/54 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); C23C 18/1637 (2013.01); C23C 18/1651 (2013.01); C23C 18/1844 (2013.01); C23C 18/32 (2013.01); C23C 18/36 (2013.01); C23C 18/42 (2013.01); H01L 21/288 (2013.01); H01L 24/03 (2013.01); C23C 18/54 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05655 (2013.01);
Abstract

In a semiconductor element of the present invention, an electroless nickel-phosphorus plating layer and an electroless gold plating layer are formed on both a front-side electrode and a back-side electrode of a front-back conduction-type substrate. The front-side electrode and the back-side electrode are formed of aluminum or an aluminum alloy. The proportion of the thickness of the electroless nickel-phosphorus plating layer formed on the front-side electrode with respect to the thickness of the electroless nickel-phosphorus plating layer formed on the back-side electrode is in a range of 1.0 to 3.5. The semiconductor element of the present invention allows the occurrence of voids inside solder during mounting by soldering to be prevented.


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