The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Sep. 05, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Kunifumi Suzuki, Yokkaichi Mie, JP;

Kazuhiko Yamamoto, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0004 (2013.01); G11C 13/0061 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 27/2463 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/144 (2013.01); G11C 2013/009 (2013.01); G11C 2013/0066 (2013.01); G11C 2013/0092 (2013.01);
Abstract

A storage device includes a first conductive layer, a second conductive layer, a first variable resistance layer, and a control circuit. The control circuit is configured to apply a first voltage between the first conductive layer and the second conductive layer for a first time and apply a second voltage less than the first voltage for a second time longer than the first time after the application of the first voltage when the first variable resistance layer is in a first high resistance state. The control circuit is further configured to apply the first voltage between the first conductive layer and the second conductive layer and apply a third voltage less than the second voltage between the first conductive layer and the second conductive layer after the application of the first voltage when the first variable resistance layer is in a first low resistance state.


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