The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2019
Filed:
Jan. 09, 2017
Applicant:
Everspin Technologies, Inc., Chandler, AZ (US);
Inventors:
Jason Janesky, Gilbert, AZ (US);
Syed M. Alam, Austin, TX (US);
Dimitri Houssameddine, Gilbert, AZ (US);
Mark Deherrera, Chandler, AZ (US);
Assignee:
Everspin Technologies, Inc., Chandler, AZ (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 11/16 (2006.01); G11C 29/12 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 17/16 (2013.01); G11C 29/021 (2013.01); G11C 29/023 (2013.01); G11C 29/026 (2013.01); G11C 29/028 (2013.01); G11C 29/12 (2013.01); G11C 29/50 (2013.01); G11C 11/16 (2013.01);
Abstract
Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.