The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Mar. 09, 2017
Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

William Lacy, Madison, WI (US);

Gregory Michael Thorson, Waunakee, WI (US);

Christopher Aaron Clark, Madison, WI (US);

Norman Paul Jouppi, Palo Alto, CA (US);

Thomas Norrie, Mountain View, CA (US);

Andrew Everett Phelps, Middleton, WI (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/302 (2018.01); G06F 15/80 (2006.01); G06F 17/16 (2006.01); G06F 7/58 (2006.01); G06N 3/063 (2006.01); G06F 9/30 (2018.01); G06F 13/36 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 7/588 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/30098 (2013.01); G06F 13/36 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G06F 15/8053 (2013.01); G06F 15/8092 (2013.01); G06F 17/16 (2013.01); G06F 15/8046 (2013.01); G06N 3/063 (2013.01);
Abstract

A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.


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