The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Sep. 11, 2017
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Inventors:

Kenichi Anzou, Kawasaki Kanagawa, JP;

Toshiaki Dozaka, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 29/12 (2006.01); G11C 29/32 (2006.01); H03K 3/037 (2006.01); G11C 29/54 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31725 (2013.01); G01R 31/3177 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 29/12015 (2013.01); G11C 29/32 (2013.01); G11C 29/54 (2013.01); G11C 2029/0403 (2013.01); G11C 2029/3202 (2013.01); H03K 3/0372 (2013.01);
Abstract

According to one embodiment, a semiconductor integrated circuit includes a logic circuit and a memory macro. The memory macro includes: a memory cell array including a memory bit cell; an output buffer; a sense amplifier configured to output data read from the memory cell array based on a first clock signal; a write driver configured to apply a write voltage; and a first register circuit that configured to fetch first input data based on a second clock signal, output the first input data to the write driver based on the second clock signal in a write operation, and outputs the first input data to the output buffer based on the first clock signal in a scan test of the logic circuit.


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