The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Jan. 16, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Raviteja Tamatam, Hyderabad, IN;

Prashant Nukala, Hyderabad, IN;

Kalyan Thota, Hyderabad, IN;

Jayant Shekhar, Hyderabad, IN;

Krishna Chaitanya Devarakonda, Hyderabad, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 9/87 (2006.01); G06K 9/46 (2006.01); G09G 5/02 (2006.01); H04N 5/272 (2006.01);
U.S. Cl.
CPC ...
H04N 9/8715 (2013.01); G06K 9/4642 (2013.01); G06K 9/4652 (2013.01); G09G 5/026 (2013.01); H04N 5/272 (2013.01); G09G 2320/0666 (2013.01); G09G 2340/125 (2013.01);
Abstract

Techniques are described for reducing the number of fetches performed when a background layer (e.g., letter or pillar box) to be displayed is of a constant fill color. One or more processors (e.g., a display processor) may be configured to detect that a background layer is of a constant fill color. If so, rather than fetching the background layer from memory, the one or more processors may be configured to generate the constant fill color for the background layer. In doing so, there may be a reduction in the number of memory fetches performed, as the constant fill background layer is not fetched or is only partially fetched. This may reduce memory fetch operations (as only the video layer is fetched) and therefore power savings (e.g., battery usage) at memory and bus interfaces, decreased use of the bandwidth at the bus and memory, and decreased processor usage.


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