The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Oct. 30, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Osamu Matsumoto, Tokyo, JP;

Fukashi Morishita, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/3745 (2011.01); H04N 5/378 (2011.01); H03M 1/76 (2006.01); H03M 1/68 (2006.01); H03M 1/46 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
H04N 5/378 (2013.01); H03M 1/46 (2013.01); H03M 1/682 (2013.01); H03M 1/765 (2013.01); H03M 1/123 (2013.01); H03M 1/466 (2013.01); H04N 5/37455 (2013.01);
Abstract

Provided is a solid-state imaging device capable of increasing the speed of an A/D converter. The solid-state imaging device includes a successive approximation A/D converter that performs A/D conversion on an analog pixel signal. The successive approximation A/D converter includes a D/A converter, a comparator, and a successive approximation register. The D/A converter converts a digital reference signal to an analog reference signal. The successive approximation register operates based on the result of comparison by the comparator to generate the digital reference signal in such a manner that the analog reference signal approximates the analog pixel signal. The D/A converter includes a split capacitor, first capacitors, second capacitors, a switch array, a third capacitor, and a multiplexer. The first capacitors each have a first electrode coupled to the output node. The second capacitors are coupled to a second electrode of the split capacitor. The switch array is coupled to a second electrode of each of the first and second capacitors and is adapted to generate the analog reference signal at the output node by selectively applying a first reference voltage. The third capacitor is coupled to the second electrode of the split capacitor. The multiplexer is coupled to a second electrode of the third capacitor and is adapted to generate the analog reference signal at the output node by selectively applying a second reference voltage.


Find Patent Forward Citations

Loading…