The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2019
Filed:
Jul. 20, 2017
Electronics and Telecommunications Research Institute, Daejeon, KR;
Woojin Chang, Daejeon, KR;
Jong-Won Lim, Daejeon, KR;
Dong Min Kang, Daejeon, KR;
Dong-Young Kim, Daejeon, KR;
Seong-il Kim, Daejeon, KR;
Hae Cheon Kim, Daejeon, KR;
Jae Won Do, Daejeon, KR;
Byoung-Gue Min, Sejong-si, KR;
Min Jeong Shin, Daejeon, KR;
Hokyun Ahn, Daejeon, KR;
Hyung Sup Yoon, Daejeon, KR;
Sang-Heung Lee, Daejeon, KR;
Jongmin Lee, Daejeon, KR;
Sungjae Chang, Daejeon, KR;
Yoo Jin Jang, Daejeon, KR;
Hyunwook Jung, Daejeon, KR;
Kyu Jun Cho, Daejeon, KR;
Hong Gu Ji, Daejeon, KR;
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon, KR;
Abstract
Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.