The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Sep. 25, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Bijesh Rajamohanan, San Jose, CA (US);

Juan Saenz, Mountain View, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/112 (2006.01); H01L 29/10 (2006.01); C01B 13/34 (2006.01); C01F 17/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1233 (2013.01); H01L 27/11273 (2013.01); H01L 29/1033 (2013.01); H01L 45/146 (2013.01); H01L 45/1608 (2013.01); C01B 13/34 (2013.01); C01F 17/0025 (2013.01);
Abstract

A method of operating a resistive memory device includes providing a resistive memory device including an array of resistive memory cells, where each of the resistive memory cells includes a resistive memory material having at least two different resistive states, performing a first mode read operation on a group of resistive memory cells within the array, determining a bit error rate for data generated by the first mode read operation, determining whether the determined bit error rate is below a predetermined limit, and performing a second mode read operation on the group of resistive memory cells within the array based on a threshold voltage if the determined bit error rate is above the predetermined limit.


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