The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Nov. 08, 2012
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Stefan Gamerith, Villach, AT;

Markus Schmitt, Neubiberg, DE;

Winfried Kaindl, Unterhaching, DE;

Gerald Sölkner, Ottobrunn, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66712 (2013.01); H01L 29/0634 (2013.01); H01L 29/0878 (2013.01); H01L 29/42368 (2013.01); H01L 29/7802 (2013.01); H01L 29/1095 (2013.01); H01L 29/41766 (2013.01); H01L 29/66727 (2013.01);
Abstract

According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C.


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