The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Jan. 12, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yong-ho Jeon, Hwaseong-si, KR;

Dae-hyun Jang, Hwaseong-si, KR;

Seung-seok Ha, Hwaseong-si, KR;

Young-ju Park, Hwaseong-si, KR;

Sun-ki Min, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/31144 (2013.01); H01L 21/3212 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 29/6656 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming dummy gate structures including a dummy gate insulating layer and dummy gate electrodes, on a first region of a semiconductor substrate, the first region including a patterning region, forming spacers on two side walls of each of the dummy gate structures, forming an interlayer insulating layer on the semiconductor substrate and the dummy gate structures, forming a protective insulating layer on a second region of the semiconductor substrate, the second region including a non-patterning region, forming a liner layer on the protective insulating layer, planarizing the interlayer insulating layer by using the liner layer as an etching mask to expose top surfaces of the dummy gate structures, forming openings by removing the dummy gate structures to expose the semiconductor substrate between the spacers, and forming gate structures including a gate insulating layer and metal gate electrodes, in the openings.


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