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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10256157 B1

PDFFull Text
Date of Patent:
Apr. 09, 2019

Filed:

Nov. 29, 2017

Method for manufacturing a si-based high-mobility cmos device with stacked channel layers, and resulting devices

Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Clement Merckling, Evere, BE;

Guillaume Boccardi, Sint-Lambrechts-Woluwe, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:

McDonnell Boehnen Hulbert & Berghoff LLP

Primary Examiner:

Mohsen Ahmadi

Assistant Examiner:

Scott E Bauman

Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 21/8238 (2006.01); H01L 21/8258 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 21/0265 (2013.01); H01L 21/02639 (2013.01); H01L 21/8258 (2013.01); H01L 21/823821 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/6681 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01); H01L 21/02543 (2013.01); H01L 21/02549 (2013.01);
Abstract

A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

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