The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2019
Filed:
Jul. 05, 2017
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Hae-Rang Choi, Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4093 (2006.01); G11C 29/12 (2006.01); G11C 11/4091 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 29/18 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/40611 (2013.01); G11C 29/1201 (2013.01); G11C 29/12005 (2013.01); G11C 29/18 (2013.01); G11C 29/50012 (2013.01); G11C 29/50016 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/5004 (2013.01);
Abstract
A memory device includes a plurality of word lines; a plurality of bit lines; a plurality of memory cells, each memory cell coupled to a corresponding word line among the plurality of word lines and a corresponding bit line among the plurality of bit lines; and a control block suitable for controlling at least two word lines among the plurality of word lines to be activated together, and determining whether or not a weak cell exists, based on a voltage of a bit line corresponding to the activated word lines.