The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Mar. 02, 2017
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-Do, KR;

Inventors:

Cholho Kim, Suwon-si, KR;

Gunwoo Yang, Seoul, KR;

Jihoon Yang, Seoul, KR;

Yongwoo Lee, Gimpo-si, KR;

Hyunyoung Choi, Seoul, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2092 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01);
Abstract

An N-th stage of a gate driver includes a first control circuit, a gate signal generating circuit, a carry signal generating circuit, a second control circuit, a third control circuit, and a holding circuit. The first control circuit controls a first signal in response to a first input signal. The gate signal generating circuit generates a gate signal in response to a clock signal and the first signal. The carry signal generating circuit generates a carry signal in response to the clock signal and the first signal. The second control circuit controls the first signal in response to a second input signal. The third control circuit generates a hold control signal in response to a third input signal having a frequency lower than the clock signal's. The holding circuit maintains levels of the first signal, the gate signal, and the carry signal in response to the hold control signal.


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