The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Dec. 22, 2017
Applicant:

Adlink Technology Inc., New Taipei, TW;

Inventors:

Hsien-Kuang Chiu, New Taipei, TW;

Peng-Yuan Chu, New Taipei, TW;

Yi-Kuo Chen, New Taipei, TW;

Chien-Chih Chen, New Taipei, TW;

Chien-Yi Hsu, New Taipei, TW;

Assignee:

ADLINK TECHNOLOGY INC., New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/12 (2006.01); G06F 13/40 (2006.01); G06F 13/36 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 13/36 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract

An intelligent PCIe slot lane assignment method applied to a motherboard including a CPU capable of providing at least 16 lanes, a switch circuit, a PCIe slot assembly consisting of a first PCIe slot, a second PCIe slot and a third PCIe slot, and a logic controller. The intelligent control of the logic controller in detection of the insertion of a PCIe expansion card in the first PCIe slot, second PCIe slot and third PCIe slot of the PCIe slot assembly enables the switch circuit to automatically assign lanes to the first PCIe slot, second PCIe slot and third PCIe slot of the PCIe slot assembly according to the detection results, increasing the convenience of expansion application and having a higher performance and expansibility.


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