The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

May. 11, 2017
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Ashish Senapati, Tempe, AZ (US);

Sean Steedman, Phoenix, AZ (US);

Brent Loertscher, Gilbert, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 1/08 (2006.01); G06F 13/40 (2006.01); G06F 9/34 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30149 (2013.01); G06F 1/08 (2013.01); G06F 9/3004 (2013.01); G06F 9/30032 (2013.01); G06F 9/30145 (2013.01); G06F 9/30167 (2013.01); G06F 9/30178 (2013.01); G06F 9/30185 (2013.01); G06F 9/342 (2013.01); G06F 13/4018 (2013.01);
Abstract

An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.


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