The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2019
Filed:
Sep. 04, 2014
Massachusetts Institute of Technology, Cambridge, MA (US);
David Joseph Whelihan, Framingham, MA (US);
Paul Stanton Keltcher, Lexington, MA (US);
Massachusetts Institute of Technology, Cambridge, MA (US);
Abstract
Global synchrony changes the way computers can be programmed. A new class of ISA level instructions (the globally-synchronous load-store) of the present invention is presented. In the context of multiple load-store machines, the globally synchronous load-store architecture allows the programmer to think about a collection of independent load-store machines as a single load-store machine. These ISA instructions may be applied to a distributed matrix transpose or other data that exhibit a high degree of data non-locality and difficulty in efficiently parallelizing on modern computer system architectures. Included in the new ISA instructions are a setup instruction and a synchronous coalescing access instruction ('sca'). The setup instruction configures a head processor to set up a global map that corresponds processor data contiguously to the memory. The 'sca' instruction configures processors to block processor threads until respective times on a global clock, derived from the global map, to access the memory.