The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2019
Filed:
Jul. 12, 2017
Applicant:
Cypress Semiconductor Corporation, San Jose, CA (US);
Inventors:
Anup Nayak, Fremont, CA (US);
Ramakrishna Venigalla, Bangalore, IN;
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); H01L 29/76 (2006.01); H01L 29/772 (2006.01); G06F 1/3287 (2019.01); G06F 13/38 (2006.01); G06F 13/42 (2006.01); G06F 1/26 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/266 (2013.01); G06F 13/385 (2013.01); G06F 13/4072 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0042 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract
Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a USB-enabled system comprises a first and second power paths and an IC controller coupled to control the first and second power paths, where the first and second power paths are external to the IC controller and the IC controller is configured to operate both an N-channel power-FET in the first power path and a P-channel power-FET in the second power path.