The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2019
Filed:
Mar. 28, 2018
Cypress Semiconductor Corporation, San Jose, CA (US);
Mohandas Sivadasan, Colorado Springs, CO (US);
Jayant Ashokkumar, Colorado Springs, CO (US);
Iulian Gradinariu, Colorado Springs, CO (US);
Abhisek Dey, Santa Clara, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
Systems, methods, and devices for providing power to low energy circuits include inrush circuits. Devices include a regulator that includes at least one driver device configured to generate a first current associated with a load comprising a low energy integrated circuit. Devices also include a bias generator configured to generate a second current to charge a load capacitor coupled with a power terminal of the low energy integrated circuit. Devices further include an enable circuit configured to enable the bias generator and disable the regulator responsive to a load voltage being below a threshold voltage, and further configured to enable the regulator to generate the first current and disable the bias generator responsive to the load voltage being above the threshold voltage.